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| bu-65552, bu-65551 and bu-65550 description the bu-65552, bu-65551 and bu-65550 provide full, intelligent interfacing between a dual redundant mil-std-1553 data bus and a pcm- cia socket. software controls these cards operation as either a 1553 bus controller (bc), remote terminal (rt), or bus monitor (mt). the bu- 65552, bu-65551 and bu-65550 are packaged in a type ii pcmcia pc card. the bu-65552 is designed around the mini-ace plus, which has backward compatability to the bu- 61586 and provides 64k x 16 on- board shared ram. using the sup- plied drivers and libraries, this card will require only 32k bytes of pc memory. the the bu-65552, bu- 65551 and bu-65550 feature ddc's bu-61586 advanced communication engine (ace). as such, it includes dual transceiver and encoder/decoder, complete 1553 pro- tocol, shared ram and memory man- agement logic for all three modes. on-board interrupt mask and interrupt status registers support flexible operation for both interrupt and polling applications. the memory management scheme for rt mode provides an option for separation of broadcast data plus a circular buffer option for individual rt subaddresses to offload the host cpu.the pcmcia interface includes 256 bytes of attribute memory as well as the four standard pcmcia card configuration registers. additional features include a wrap-around built-in-test, and soft- ware programmable rt address selection. free c runtime library and comprehensive menu applications for dos, windows 95/98 and windows nt. these cards support all dual redundant mode codes and message formats. additionally, these cards allow the use of commercial off-the- shelf or ruggedized laptop and note- book computers in applications requiring a mil-std-1553 interface. full compliance with both mil-std- 1553 and pcmcia 2.10 make the bu-65552, bu-65551 and bu-65550 an excellent choice for real-time sim- ulation, test, and system integration applications. mil-std-1553 bc/rt/mt interface card bd15..bd? d15..d? a15..a? vcc gnd cd1, cd2 bu-61586 ace 1553 bc/rt/mt 1553 bus card configuration registers attribute memory pcmcia interface adapter clock oscillator 68 pin card connector socket ce1, ce2, we/pgm, iord, iqwr, reset, reg, oe rdyb, sy/ireq, inpack, wp/iois16, bvd1/stschg, bvd2/spkr, wait ? 1994, 1999 data device corporation figure 1. bu-65552, bu-65551 and bu-65550 block diagram features ? type ii pcmcia 2.10 compatible pc card mil-std-1553 dual redundant bc\rt\mt with simultaneous rt/monitor multiprotocol support of mil-std-1553a and b notice 2 flexible rt data buffering selective message monitor 64k x 16 shared ram (bu-65552) 4k x 16 shared ram (bu-65551) 12k x 16 shared ram (bu-65550) runtime libraries for windows 3.1, windows 95/98 and windows nt menu software for windows 3.1, windows 95/98 and windows nt bu-65550 supplied with ddc-57612-1 interface cable bu-65551 supplied with ddc-57613-1 interface cable bu-65552 supplied with ddc-70093-1 interface cable
2 functional overview general the bu-65552, bu-65551 and bu-65550 (see figure 1) pro- vides a user-friendly interface between the serial mil-std-1553 bus and a pcmcia interface socket. the operating modes of these cards are controlled through the use of 24 on-board regis- ters. 1553 message traffic is stored and retrieved using the ded- icated, memory mapped, on-board 12k words of ram. the var- ious registers control and operate the bu-65552, bu-65551 and bu-65550. they include the five configuration registers, start/reset register, time tag register, interrupt mask register, and interrupt status register. the configuration registers define the operating mode and memory management features. the start/reset register provides various reset and bc/mt start functions. the interrupt mask register enables desired interrupts, with the interrupt priority level being jumper programmable by the user. the cause of interrupts may be determined by a single read operation, by means of the interrupt status register. the time tag register features pro- grammable resolution and is used to time tag messages in bc, rt, or mt modes. the bu-65552 64k x16 of static ram is shared by the pc host and the 1553 bus with memory arbitration handled automatical- ly by the bu-65552. the bu-65551 4k x16 of static ram is shared by the pc host and the 1553 bus with memory arbitration handled automatical- ly by the bu-65551. the bu-65550 12k x16 of static ram is shared by the pc host and the 1553 bus with memory arbitration handled automatical- ly by the bu-65550. the bu-65552, bu-65551 and bu-65550 will withhold the wait signal (assert to logic "0") to the pcmcia socket interface while a word is being transferred to or from the 1553 bus. since the memory arbitration is handled by simply stretching the hand- shake cycle, the wait state is transparent to the pc host proces- sor's software. a maximum wait of 2.6 s can occur notes: (1) typical value for minimum intermessage gap time. under software control, may be lengthened to (65,535 ms minus message time), in increments of 1 s. (2) software programmable (4 options). includes rt-to-rt timeout (mid-parity of transmit command to mid-sync of transmitting rt status). parameter min typ absolute maximum ratings +5 v supply voltage -0.3 7.0 v receiver threshold voltage, transformer coupled, measured on stub common mode voltage 0.200 0.860 10 v p - p v peak 6 18 -90 100 7 20 9 27 10 90 300 4 17.5 21.5 49.5 127 0 -20 -25 -55 0 -20 4.5 7 19.5 23.5 51.5 129 55 65 70 80 55 65 0.55 1.18 1.81 3.07 5.5 110 300 490 860 sec sec sec sec sec sec sec sec c c c c c c w w w w v ma ma ma ma 2.5 9.5 18.5 22.5 50.5 128 668 0.4 0.98 1.16 1.47 units v p - p v p - p mv p - p , diff mv nsec 80 225 385 700 1553 message timing rt response time completion of cpu write (bc start-to start of first bc message) bc intermessage gap (see note 1) bc/rt/mt response timeout (see note 2) ! 18.5 nominal ! 22.5 nominal ! 50.5 nominal ! 128.0 nominal transmitter watchdog timeout max transmitter differential output voltage ! direct coupled across 35 ohms, measured on bus ! transformer coupled, measured on stub output noise, differential (direct coupled) output offset voltage, direct coupled across 35 ohms rise/fall time power supply requirements voltages/tolerances ! + 5 v current drain @ + 5.0 v ! idle ! 25% transmitter duty cycle ! 50% duty cycle ! 100% duty cycle power dissipation total pc card (v cc = +5.0 v) ! idle ! 25% duty cycle ! 50% duty cycle ! 100% duty cycle software requirements ! card services driver compliant to pcmcia release 2.10 or higher hardware requirements ! socket interface compliant with pcmcia release 2.10 or higher table 2. host system requirements table 1. bu-65552, bu-65551 and bu-65550 specifications thermal bu-65552 operating temperature storage temperature bu-65551 operating temperature storage temperature bu-65550 operating temperature storage temperature vibration shock operating humidity non-operating humidity random vibration, 0.1 g 2 / hz from 20 hz to 2000 hz 40g, 11ms, half sine 0 to 95% non-condensing 100% condensing table 1. bu-65552, bu-65551 and bu-65550 specifications (continued) in (mm) oz (gm) 2.8 (80) physical characteristics size weight units max typ min parameter 3.370 x 2.126 x 0.197 (85.6 x 54.0 x 5.0) in addition to storing the 1553 message data, the ram imple- ments the stacks and look-up tables required for the different modes of operation. a global double buffering mechanism is available to prevent partially updated information from being transferred to or from the 1553 bus. for rt mode, there is a pro- grammable option to separate broadcast message data from non-broadcast data. this provides compliance to mil-std- 1553. in addition, for rt mode, there is the choice of storing either a single message, a double buffer data structure, or a cir- cular buffer data structure. the size of the circular buffer is pro- grammable up to 8192 words, on a tx/rx/bcst-subaddress basis. the bu-65552, bu-65551 and bu-65550 support programma- ble command illegalization for rt mode. this allows individual command words to be illegalized as a function of bit, sub- address, and word count/mode code. since the illegalization scheme is ram based, it is inherently self-testable. a descriptor stack or command stack is maintained for bc, rt, and mt modes. this records the status of each message, the time the message was transmitted or received, and contains either the received 1553 command and data block pointer (in rt or mt mode) or the actual address of the 1553 message block (in bc mode). in rt mode, a lookup table is provided to store the addresses of the data blocks to be used when receiv- ing or transmitting messages for the individual subaddresses. the pc cards rt mode is multiprotocol, supporting mil-std- 1553a, mil-std-1553b notice 2, stanag 3838 (including efa bus), and the mcair a3818, a5232, and a5690 protocols. the bu-65552, bu-65551 and bu-65550 implement three mon- itor modes: a word monitor, a selective message monitor, and a combined rt/selective message monitor. pcmcia interface the bu-65552, bu-65551 and bu-65550 provide a card information structure (cis) within the attribute memory space of the pcmcia interface. the cis contains device configuration information structures called basic compatibility tuples. the for- mat of these configuration tuples is defined within the pcmcia interface standard. in addition to the cis there are the four stan- dard pcmcia configuration registers (configuration option register, card configuration and status register, pin replacement register, and socket and copy register). the cis, also referred to as the metaformat, provides a level of device information which allows a card resource manager or an application program to identify and fully configure the card. memory management the bu-65552, bu-65551 and bu-65550 incorporate complete memory management and processor interface logic. the soft- ware interface to the host processor is implemented by means of 24 on-board registers plus up to 64k words of ram. for all three modes, a stack area of ram is maintained. in bc mode, the stack allows for the scheduling of multimessage frames. for all three modes, the stack provides a real-time chronology of all r / t messages processed. in addition to the stack processing, the memory management logic performs storage, retrieval, and manipulation functions involving pointer and message data structures for all three modes. the bu-65552, bu-65551 and bu-65550 provide a number of programm-able options for rt mode memory management. in compliance with mil-std-1553, received data from broadcast messages may be optionally separated from nonbroadcast received data. for each transmit, receive or broadcast subad- dress, either a single-message data block or a variable-sized (128 to 8192 words) circular buffer may be allocated for data storage. in addition to helping ensure data consistency, the cir- cular buffer feature provides a means of greatly reducing host processor overhead for bulk data transfer applications. end-of- message interrupts may be enabled either globally, following error messages, on a tx/rx/bcst-subaddress basis, or when any particular tx/rx/bcst-subaddress circular buffer reaches its lower boundary. interrupts the bu-65552, bu-65551 and bu-65550 provide many pro- grammable options for interrupt generation and handling. the interrupt output pin ( ) has three software programmable modes of operation: a pulse, a level output cleared under soft- ware control, or a level output automatically cleared following a read of the interrupt status register. individual interrupts are enabled by the interrupt mask register. the host processor may easily determine the cause of the inter- rupt by using the interrupt status register. the interrupt status register provides the current state of the interrupt conditions. the interrupt status register may be updated in two ways. in the standard interrupt handling mode, a particular bit in the interrupt status register will be updated only if the condition exists and the corresponding bit in the interrupt mask register is enabled. in the enhanced interrupt handling mode, a particular bit in the interrupt status register will be updated if the condition exists regardless of the contents of the corresponding interrupt mask register bit. in any case, the respective interrupt mask register bit enables an interrupt for a particular condition. the bu-65552, bu-65551 and bu-65550 provide maskable interrupts and 15-bit interrupt status register for end of mes- sage, end of bc message list, erroneous messages, status set (bc mode), time tag register rollover, rt address parity error conditions, bc retry, data stack rollover, command stack rollover, transmitter watchdog timeout, or ram parity error. the interrupt status register allows the host processor to determine the cause of all interrupts by means of a single read operation. internal command illegalization the bu-65552, bu-65551 and bu-65550 implemen internal command illegalization for rt mode. the illegalization architec- ture allows for any subset of the 4096 possible combinations of broadcast/own address, bit, subaddress, and word count/mode code to be illegalized. the illegalization scheme is under software control of the host processor. as a result, it is inherently self-testable. r / t int 3 internal time tag the bu-65552, bu-65551 and bu-65550 include an internal read/writable time tag register. this register is a cpu read/writable 16-bit counter with a programmable resolution of either 2, 4, 8, 16, 32, or 64 s per lsb. another option allows the time tag register to be incremented under software control. this supports self-test for the time tag register. for each message processed, the value of the time tag regis- ter is loaded into the second location of the respective descrip- tor stack entry ("time tag word") for both bc and rt modes. additional options are provided to clear the time tag register following a synchronize (without data) mode command or load the time tag register following a synchronize (with data) mode command. another option enables an interrupt request and a bit in the interrupt status register to be set when the time tag register rolls over from ffff to 0000 (hex). assuming the time tag register is not loaded or reset, this will occur at approxi- mately 4-second time intervals, for 64 s/lsb resolution, down to 131 ms intervals, for 2 s/lsb resolution. another programmable option for rt mode is for the service request status word bit to be automatically cleared following the pc cards response to a transmit vector word mode com- mand. addressing, internal registers, memory management, and interrupts addressing these cards all internal pointers used by these cards are assumed to be word addresses, however byte addressing is used by the pc to access memory and registers in the card. for example, to access the the area a stack pointer at word offset address 0100 (hex), a byte address offset of 0200 (hex) must be used (i.e. the byte address is determined by multiplying the word address by two). the shared ram space starts at byte location 8000 if the mem- ory allocation were contiguous. the registers are mapped into memory locations 0x0000 through 0x002f. the memory address space between 0x0030 and 0x7fff is reserved. the 64k x 16 ram uses page swapping, which is done in the device driver. common memory address map the software interface of the bu-65552, bu-65551 and bu- 65550 to the host processor consists of 17 internal operational registers for normal operation, an additional 8 test registers, plus shared memory (64k x 16 for bu-65552, 4k x 16 for bu-65551 and 12k x 16 for bu-65550). both the registers and the shared memory reside in the pcmcia common memory space. see table 3. the bitmaps of the 17 internal registers are shown in tables 4 through 21. definition of the address mapping and accessibility for the bu- 65552, bu-65551 and bu-65550 17 nontest registers, and the test registers, is as follows: interrupt mask register: used to enable and disable interrupt requests for various conditions. configuration registers #1 and #2: used to select the pc cards mode of operation, and for software control of rt status word bits, active memory area, bc stop-on-error, rt memory management mode selection, and control of the time tag oper- ation. 4 table 3. common memory address mapping hex address description/accessibility interrupt mask register (rd/wr) 0002, 0003 configuration register # 1 (rd/wr) 0004, 0005 configuration register # 2 (rd/wr) 0004, 0005 configuration register # 2 (rd/wr) 0006, 0007 start/reset register (wr) 0006, 0007 bc/rt command stack pointer register (rd) 0008, 0009 0016, 0017 000a, 000b bc frame time remaining register (rd)* time tag register (rd/wr) 0018, 0019 000c, 000d bc time remaining to next message register (rd)* interrupt status register (rd) 001a,001b 000e, 000f 001c, 001d 0010, 0011 rt status word register (rd) configuration register #4 001e, 001f 0012, 0013 reserved ? ? ? reserved reserved ? ? ? reserved configuration register #5 0014, 0015 12k x 16 shared ram (rd/wr) see note below. ? ? ? 12k x 16 shared ram (rd/wr) data stack address register (rd/wr) rt bit word register (rd) test mode register 0 ? ? ? test mode register 7 e000, e001 ? ? ? fffe, ffff configuration register #3 0000, 0001 bc control word/rt subaddress control word register (rd/wr) bc frame time*/rt last command/mt trigger word* register (rd/wr) 0030, 0031 ? ? ? 7ffe, 7fff 8000, 8001 ? ? ? dffe, dfff 0020, 0021 ? ? ? 002e,002f notes: 1. normally ram addresses will be defined as an offset from the base address 2. bu-65551 shared ram is 4k x 16 start/reset register: used for "command" type functions, such as software reset, bc/mt start, interrupt reset, time tag reset, and time tag register test. the start/reset register includes provisions for stopping the bc in its auto-repeat mode, either at the end of the current message or at the end of the cur- rent bc frame. bc/rt command stack pointer register: allows the host cpu to determine the pointer location for the current or most recent message when the pc card is in bc or rt mode. bc control word/rt subaddress control word register: in bc mode, allows host access to the current or most recent bc control word. the bc control word contains bits that select the active bus and message format, enable off-line self-test, mask- ing of status word bits, enable retries and interrupts, and spec- ify mil-std-1553a or -1553b error handling. in rt mode, this register allows host access to the current or most recent subaddress control word. the subaddress control word is used to select the memory management scheme and enable interrupts for the current message. the read/write accessibility can be used as an aid for testing the ace. time tag register: maintains the value of a real-time clock. the resolution of this register is programmable from among 2, 4, 8, 16, 32, and 64 s/lsb. the tag_clk input signal also may cause an external oscillator to clock the time tag register. start-of-message (som) and end-of-message (eom) sequences in bc, rt, and message monitor modes cause a write of the current value of the time tag register to the stack area of ram. interrupt status register: mirrors the interrupt mask register and contains a master interrupt bit. it allows the host processor to determine the cause of an interrupt request by means of a sin- gle read operation. configuration registers #3, #4, and #5: used to enable many of the bu-65552, bu-65551 and bu-65550 advanced features. these include all the enhanced mode features; that is, all the functionality beyond that of the previous generation product, the bus-65529 that makes use of the advanced integrated mux hybrid with enhanced rt features (aim-hy'er). for all three modes, use of the enhanced mode enables the various read- only bits in configuration register #1. for bc mode, the enhanced mode features include the expand- ed bc control word and bc block status word, additional stop- on-error and stop-on-status set functions, frame auto-repeat, programmable intermessage gap times, automatic retries, expanded status word masking, and the capability to generate interrupts following the completion of any selected message. for rt mode, the enhanced mode features include the expand- ed rt block status word, the combined rt/selective message monitor mode, internal wrapping of the " " output signal (from the j' chip)to the " " rt status word bit, the double buffering scheme for individual receive (broadcast) subaddress- es, and the alternate (fully software programmable) rt status word. for mt mode, use of the enhanced mode enables use of the selective message monitor, the combined rt/selective monitor modes, and the monitor triggering capability. data stack address register: used to point to the current address location in shared ram used for storing message words (second command words, data words, rt status words) in the selective word monitor mode. frame time remaining register: provides a read only indi- cation of the time remaining in the current bc frame. the reso- lution of this register is 100 s/lsb. message time remaining register: provides a read only indi- cation of the time remaining before the start of the next message in a bc frame. the resolution of this register is 1 s/lsb. bc frame/rt last command/mt trigger word register: in bc mode, it programs the bc frame time for use in the frame auto-repeat mode. the resolution of this register is 100 s/lsb, with a range of 6.55 seconds. in rt mode, this register stores the current (or most previous) 1553 command word processed by the ace rt; in the word monitor mode, this register specifies a 16-bit trigger (command) word. the trigger word may be used to start or stop the monitor, or to generate interrupts. status word register and bit word registers: provide read- only indications of the bu-65552, bu-65551 and bu-65550 rt status and bit words. test mode registers 0-7: these registers may be used to facil- itate built-in testing of the bu-65552, bu-65551 and bu-65550 . rtflag rtfail 5 each of the operating modes, bus controller (bc), remote terminal (rt), and monitor terminal (mt) can be setup independently wi th all parameters being saved to an ace setup file (*.ace). the card is only capable of running in one mode at a time. each mode has its own run screen. the ace menu is provides the necessary functionality for creating messages and assembling the messages into a frame for use by the bc function. the parameters for each message, including the command word, data words, and bus selection are modifiable fro m the ace menu . setup screens are available for setting other operational parameters such as response timeout, retries and stop - on criteria. adding these messages to a frame structure creates a bc frame. the ace menu allows a frame to be a composition of many minor frames, where each minor frame will represent the same amount of time, but is not restricted to the same number of m es- sages. the minor frame time is operator programmable. the number of minor frames times the minor frame time represents the ma jor frame time. once the frame is complete, the bc run screen can be used to control the processing of the bc frame. this screen displays operational status and provides controls for setting the minor frame time, the number of frames to send, and communica tion stack setup. the stack setup allows the user to set the name and size of the stack. the stack file where the 1553 bus traffic will be stored, and may be viewed at a later time. ace software the bu-65552/bu-65551/bu-65550 are supplied with software runtime libraries for dos, windows 3.1, windows 95/98 and windows nt, and menu programs for windows 3.1, windows 95/98 and windows nt. this software is provided with the card at no extra cost. ace menu overview the ace menu provides an interface for all ace bc/rt/mt cards. for detailed information about the ace menu, please refer to th e ace menu user's guide. 6 figure 2. ace setup window 7 communication information is saved in stack files (*.asf). the run screens allow configuration of the stack file location and s ize. all run modes provide the stack view capability. after running the card, the generated stack file can be viewed by opening the stack v iewer. within each of the operating mode tool bars and menus, there is an open stack button that allows quick access to the stack file open dialog. once opened, the stack file can be searched for any type of message or error. these stack files are compatible with th e pre- vious version stack files for both the windows 95 and windows 3.xx ace menu programs. the remote terminal mode operation allows setting the hardware to respond to a specified rt address. the setup for a rt is much simpler than that of a bc. the bulk of the setup is used to specify the data that should be returned based on the sub-address set in the message command word. the data edit screen provides controls to select the sub-address and enter the data. once all of th e sub-address responses have been determined, the operation of the rt is controlled in the setup screen. the controls available here are the rt address, remote terminal to remote terminal timeout, and status word bits set. finally, the rt run screen will prov ide options for setting the remote terminal address, and the stack file. figure 3. bc run dialog window figure 4. rt run dialog window monitor operation is also provided. the ace menu monitor is a full message monitor that will monitor the 1553 bus traffic, dec ode the messages (command and data) and save the information to a stack file. the monitor is capable of filtering the message informat ion based on remote terminal address, sub-address, and transmit/receive for each message. when all of the appropriate filtering ha s been established, the response timeout option may be set. the timeout option instructs the monitor as to how long it must wait before declaring a no response message. the run monitor screen has controls that allow setting the stack file requirements, and to p ro- vide access to the monitor trigger capabilities. the monitor is capable of triggering its capture based on any combination of the com- mand word bits, or based on any of the error bits in the rt status word. 8 figure 6. monitor mode - stack view ace runtime libraries the runtime libraries come in both 16-bit and 32-bit versions to support 16 and 32 bit dos and windows. using the runtime libr ary, applications may be created that are capable of controlling the pcmcia card in either the bc, rt or mt mode. the newest versio n of this runtime library supports c and visual basic programming. included with the ace runtime library are sample applications for bus controller, remote terminal, and monitor mode control. there are also sample programs for self-test and loop back tests. the self-test program tests and reports any errors found with the major portions of the hardware including registers, ram, interrup t gen- eration, and the protocol unit. the loop back tests force the bu-65552|bu-65551|bu-65550 card to communicate with itself. thi s test verifies the protocol unit and the transceivers to a greater degree than is performed by the selftst2 program. the source for all of the test and sample programs is provided free of charge. these source programs may be used as a starting point for custom applica- tions. the following source code represents the simplicity of writing code for the bu-6555x pcmcia cards. this program sends 10 words of data to rt 1 sub-address 5 on channel a, followed by a 32 word transmit to rt 6 sub-address 1 on channel 'a'. it then recei ves 5 the stack file can be searched by message command word, any data word, or any mil-std-1553 error. each of the search criteria may be combined with a mask to allow searching for a family of command or data words. the search direction is selectable betwe en up and down. finally, a stack view capability is provided for each of the modes (bc, rt, and mt). from the stack button, a stack file can b e select- ed, and viewed on the screen. once the stack file is displayed, there is a capability of 'finding' any message that was captur ed. the stack file contains information pertaining to the storage date, time and number of messages. it also contains the data portion of the messages, all pertinent status information, and text describing the error type. figure 5. monitor mode window 9 words from rt 8 sub-address 4 on channel 'a', followed by a 32 word receive from rt 7 sub-address 2 on channel 'a'. note that the creation of a 32 word message requires only that the data be defined in a buffer, and then a single function call to busenddata (?) be made. similarly, to receive data from a rt, a buffer must be defined, and a call to bugetdata(?) will be made. this encaps u- lated functionality relieves the application developer from having to know the dirty details of the 1553 protocol hardware and registers. the following code is from the bcdemo1.c sample program supplied with the bu-6555x hardware. #include 10 table 5. configuration register #1 (read/write 02h) bit bc function ( enhanced mode only bits 11-0) rt without alternate status rt with alternate status (enhanced only) monitor function (enhanced mode only bits 12-0) 15 (msb) rt/bc-mt (logic 0) (logic 1) (logic 1) (logic o) 14 mt/bc-rt (logic 0) (logic 0) (logic 0) (logic 1) 13 current area b/a current area b/a current area b/a current area b/a 12 message stop-on-error message monitor enabled (mmt) message monitor enabled (mmt) message monitor enabled (mmt) 11 frame stop-on-error dynamic bus control acceptance s10 trigger enabled word 10 status set stop-on-message busy s09 start-on-trigger 9 status set stop-on-frame service request s08 stop-on-trigger 8 frame auto-repeat subsystem flag s07 not used 7 external trigger enabled rtflag (enhanced mode only) s06 external trigger enabled 6 internal trigger enabled not used s05 not used 5 intermessage gap timer enabled not used s04 not used 4 retry enabled not used s03 not used 3 doubled/single retry not used s02 not used 2 bc enabled not used s01 monitor enabled(read only) 1 bc frame in progress (read only) not used s00 monitor triggered (read only) 0 (lsb) bc message in progress (read only) rt message in progress (enhanced mode only, read only) rt message in progress (read only) monitor active (read only) 3 bc end of frame 2 table 4. interrupt mask register (read/write 00h) format error bit description 1 15 (msb) reserved status set 14 ram parity error 0 (lsb) 13 transmitter timeout end of message 12 bc/rt command stack rollover 11 mt command stack rollover 10 mt data stack rollover 9 rt mode code/mt pattern trigger 8 bc retry 7 rt address parity error 6 time tag rollover 5 rt circular buffer rollover 4 rt subaddress control word eom separate broadcast data 0 (lsb) enhanced rt memory management 1 clear service request 2 level/pulse* interrupt request 3 interrupt status auto clear 4 load time tag on synchronize 5 clear time tag on synchronize 6 time tag resolution 0 (ttr0) 7 time tag resolution 1 (ttr1) 8 time tag resolution 2(ttr2) 9 256-word boundary disable 10 overwrite invalid data 11 rx sa double buffer enable 12 busy lookup table enable 13 logic ?0? 14 enhanced interrupts 15 (msb) description bit table 6. configuration register #2 (read/write 04h) reset 0 (lsb) bc/mt start 1 interrupt reset 2 time tag reset 3 time tag test clock 4 bc stop-on-frame 5 bc/mt stop-on-message 6 reserved 7 ? ? ? ? ? ? reserved description bit table 7. start/reset register (write 06h) 11 command stack pointer 0 0 (lsb) ? ? ? ? ? ? command stack pointer 15 description bit table 8. bc/rt command stack pointer reg. (read 06h) rt-rt format 0 (lsb) broadcast format 1 mode code format 2 subsys flag bit mask 1553a/b select 3 eom interrupt enable 4 mask broadcast bit 5 off line self test 6 bus channel a/b 7 retry enabled 8 reserved bits mask 9 terminal flag bit mask 10 subsys busy bit mask 12 service request bit mask 13 m.e. mask 14 reserved description bit 11 table 9. bc control word register (read/write 08h) bcst: memory management 0 (mm0) 0 (lsb) bcst: memory management 1 (mm1) 1 bcst:memory management 2 (mm2) 2 tx: memory management 1 (mm1) bcst: circ buf int 3 bcst: eom int 4 rx: memory management 0 (mm0) 5 rx: memory management 1 (mm1) 6 rx: memory management 2 (mm2) 7 rx: circ buf int 8 rx: eom int 9 tx: memory management 0 (mm0) 10 tx: memory management 2 (mm2) 12 tx: circ buf int 13 tx: eom int 14 rx: double buffer enable description bit 11 table 10. rt subaddress control word register (read/write 08h) table 11. time tag register (read/write 0ah) bit description time tag 15 ? ? ? ? ? ? 0 (lsb) time tag 0 15 (msb) 15 (msb) 15 (msb) 15 (msb) 15 (msb) 12 end of message 0 (lsb) status set 1 format error 2 mt command stack rollover bc end of frame 3 rt subaddress control word eom 4 rt circular buffer rollover 5 time tag rollover 6 rt address parity error 7 bc retry 8 rt mode/mt pattern trigger 9 mt data stack rollover 10 bc/rt command stack rollover 12 transmitter timeout 13 ram parity error master interrupt description bit 11 table 12. interrupt status register (read/write 0ch) enhanced mode code handling 0 (lsb) 1553a mode codes enable 1 raft-flag wrap enable 2 mt command stack size 0 busy rx transfer disable 3 illegal rx transfer disable 4 alternate status word enable 5 override mode t/r error 6 illegalization disabled 7 mt data stack size 0 8 mt data stack size 1 9 mt data stack size 2 10 mt command stack size 1 12 bc/rt command stack size 0 13 bc/rt command stack size 1 14 enhanced mode enable description bit 11 table 13. configuration register #3 (read/write 0eh) test mode 0 0 (lsb) test mode 1 1 test mode 2 2 broadcast mask enable/xor latch rt address with config #5 3 mt tag gap option 4 valid busy/no data 5 valid m.e./no data 6 2nd retry alt/same bus 7 1st retry alt/same bus 8 retry if status set 9 retry if -a and m.e. 10 expanded bc control word enable 12 mode command override busy 13 inhibit bit word if busy 14 external bit word enable description bit 11 table 14. configuration register #4 (read/write1 0h) rt address parity 0 (lsb) rt address 0 1 rt address 1 2 expanded crossing enabled rt address 2 3 rt address 3 4 rt address 4 5 logic ?1? 6 broadcast disabled 7 gap check enabled 8 response timeout select 0 9 response timeout select 1 10 external tx inhibit b, read only bu-65170/61580x6 12 external tx inhibit a, read only bu-65170/61580x6 13 logic ?0? 14 12mhz clock select description bit 11 table 15. configuration register #5 (read/write 12h) 15 (msb) 15 (msb) 15 (msb) 15 (msb) 14 13 monitor data stack address 0 0 (lsb) ? ? ? ? ? ? monitor data stack address 15 15 (msb) description bit table 16. monitor data stack address register (read/write 14h) note: resolution = 100 s per lsb bc frame time remaining 0 0 (lsb) ? ? ? ? ? ? bc frame time remaining 15 description bit table 17. bc frame time remaining register (read/write 16h) note: resolution = 1 s per lsb bc message time remaining 0 0 (lsb) ? ? ? ? ? ? bc message time remaining 15 description bit table 18. bc message time remaining register (read 18h) bit 0 0 (lsb) ? ? ? ? ? ? bit 15 description bit table 19. bc frame time/rt last command/mt trigger register (read/write 1ah) terminal flag 0 (lsb) dynamic bus control accept 1 subsystem flag 2 rt address 0 busy 3 broadcast command received 4 reserved 5 reserved 6 reserved 7 service request 8 instrumentation 9 message error 10 rt address 2 13 rt address 3 14 rt address 1 12 rt address 4 15 (msb) description bit table 20. rt status register (read 1ch) command word contents error 0 (lsb) rt-rt 2nd command word error 1 rt-rt no response error 2 transmitter shutdown b rt-rt gap/synch/address error 3 parity/manchester error received 4 incorrect sync received 5 low word count 6 high word count 7 channel b/a 8 terminal flag inhibited 9 transmitter shutdown a 10 handshake failure 12 loop test failure a 13 loop test failure b 14 transmitter timeout 15 (msb) description bit 11 table 21. rt bit word register (read 1eh) 15 (msb) 15 (msb) 15 (msb) 11 14 command word contents error 0 (lsb) rt-rt 2nd command error 1 rt-rt gap/sync/address error 2 rt-rt format invalid word 3 incorrect sync 4 word count error 5 illegal command word 6 data stack rollover 7 loop test fail 8 no response timeout 9 format error 10 error flag 12 channel b/a 13 som 14 eom description bit 11 table 23. rt mode block status word gap time mode code 0 (lsb) contiguous data/gap 1 channel b/a 2 command/data 3 error 4 broadcast 5 this rt 6 word flag 7 ? ? ? ? ? ? gap time description bit 8 table 24. word monitor identification word command word contents error 0 (lsb) rt-rt 2nd command error 1 rt-rt gap/sync/address error 2 rt-rt transfer invalid word 3 incorrect sync 4 word count error 5 reserved 6 data stack rollover 7 good data block transfer 8 no response timeout 9 format error 10 error flag 12 channel b/a 13 som 14 eom 15 (msb) description bit 11 table 25. message monitor mode block status word table 22. bc mode block status word 11 bit description 15 (msb) eom 14 som 13 channel b/a 12 error flag 10 format error 9 no response timeout 8 loop test fail 7 masked status set 6 retry count 1 5 retry count 0 4 good data block transfer 3 wrong status address/no gap status set 2 word count error 1 incorrect sync type 0 (lsb) invalid word tables 22 to 25 are not registers, but they are words stored in ram: 15 (msb) 15 (msb) bus controller (bc) architecture the bc protocol of the bu-65552, bu-65551 and bu-65550 implement all mil-std-1553b message formats. message for- mat is programmable on a message-by-message basis by means of bits in the bc control word and the bit of the command word for the respective message. the bc control word allows 1553 message format, 1553a/b type rt, bus chan- nel, self-test, and status word masking to be specified on an individual message basis. in addition, automatic retries and/or interrupt requests may be enabled or disabled for individual mes- sages. the bc performs all error checking required by mil-std- 1553b. this includes validation of response time, sync type and sync encoding, manchester ii encoding, parity, bit count, word count, status word rt address field, and various rt-to-rt transfer errors. the bc response timeout value is programma- ble with choices of 18, 22, 50, and 130 s. the longer response timeout values allow for operation over long buses and/or the use of repeaters. figure 7 illustrates bc intermessage gap and frame timing. the bu-65552, bu-65551 and bu-65550 may be programmed to process bc frames of up to 512 messages with no processor intervention. it is possible to program for either single frame or frame auto-repeat operation. in the auto-repeat mode, the frame repetition rate may be controlled either internally, using a pro- grammable bc frame timer, or from an external trigger input. the internal bc frame time is programmable up to 6.55 seconds in increments of 100 s. in addition to bc frame time, intermessage gap time, defined as the start of the current message to the start of the subsequent message, is programmable on an individual message basis. the time between individual successive mes- sages is programmable up to 65.5 ms, in increments of 1 s. bc memory organization table 26 illustrates a typical memory map for bc mode. it is important to note that the only fixed locations for the bu-65552, bu-65551 and bu-65550 in the standard bc mode are for the two stack pointers (address locations 0100 [hex] and 0104) and for the two message count locations (0101 and 0105). enabling the frame auto-repeat mode will reserve four more memory locations for use in the enhanced bc mode; these locations are for the two initial stack pointers (address locations 102 [hex] and 106) and for the initial message count locations (103 and 107). the user is free to locate the stack and bc message blocks any- where else within the shared ram address space. r / t for simplicity of illustration, assume the allocation of the maxi- mum length of a bc message for each message block in the typ- ical bc memory map of table 26. the maximum size of a bc message block is 38 words, for an rt-to-rt transfer of 32 data words (control + 2 commands + loopback + 2 status words + 32 data words). note, however, that this example assumes the disabling of the 256-word boundaries. 15 figure 7. bc message gap and frame timing message no. 1 message no. 2 message no. 1 intermessage gap time for message no. 1 bc frame time stack b 2f00-2fff not used 2ee6-2eff message block 308message block 8 2ec0-2ee5 ? ? ? ? initial message count a (see note) (auto-frame repeat mode) ? ? message block 2 0154-0179 message block 1 012e-0153 message block 0 0108-012d initial message count b (see note) (auto-frame repeat mode) 0107 initial stack pointer b (see note) (auto-frame repeat mode) 0106 message count b 0105 stack pointer b 0104 initial stack pointer a (see note) (auto-frame repeat mode) 0102 message count a (fixed location) 0101 stack pointer a (fixed location) 0100 stack a 0000-00ff description address (hex) 0103 table 26. typical bc memory organization (shown for 12k ram) notes: 1) used only in the enhanced bc mode with frame auto-repeat enabled. 2) address represents the word offset from the memory base address in the common memory address space. 3) for the 65552, the memory spans from 0000(hex) to ffff(hex), providing a full 64k words of shared ram. bc memory management figure 8 illustrates the bu-65552, bu-65551 and bu-65550 bc memory management scheme. one of the bc memory man- agement features is the global double buffering mechanism. this provides for two sets of the various bc mode data structures: stack pointer and message counter locations, descriptor stack areas, and bc message blocks. bit 13 of configuration register #1 selects the current active area. at any point in time, internal 1553 memory management logic may access only the various data structures within the "active" area. figure 8 delineates the "active" and "inactive" areas by the non-shaded and shaded areas, respectively; however, both the "active" and "nonac- tive" areas are always accessible by the host processor. in most applications, the host processor will access the "nonactive" area, while the 1553 bus processes the "active" area messages. the bc may be programmed to transmit multimessage frames of up to 512 messages. the number of messages to be processed is programmable by the active area message count location in the shared ram, initialized by the host processor. in addition, the host processor must initialize another location, the active area stack pointer. the stack pointer references the four-word message block descriptor in the stack area of shared ram for each message to be processed. the bc stack size is programmable with choices of 256, 512, 1024, and 2048 words. in the bc frame auto-repeat mode, the initial stack pointer and initial message counter locations must be loaded by the host prior to the processing of the first frame. the single frame mode does not use these two locations. the third and fourth words of the bc block descriptor are the intermessage gap time and the message block address for the respective message. these two memory locations must be writ- ten by the host processor prior to the start of message process- ing. use of the intermessage gap time is optional. the block address pointer specifies the starting location for each message block. the first word of each bc message block is the bc control word. at the start and end of each message, the block status and time tag words write to the message block descriptor in the stack. the block status word includes indications of message in process or message completion, bus channel, status set, response timeout, retry count, status address mismatch, loop test (on-line self-test) failure, and other error conditions. table 22 illustrates the bit mapping of the bc block status word. the 16-bit time tag word will reflect the current contents of the inter- nal time tag register. this read/writable register, which oper- ates for all three modes, has programmable resolution of from 2 to 64 s/lsb. in addition, the time tag register may be clocked from an external source. 16 figure 18. bc mode memory management 15 13 0 current area b/a configuration register initial stack pointers (note) initial message counters (note) message counters stack pointers block status word time tag word intermessage gap time word message block addr descriptor stacks message blocks message block message block note: initial stack pointers and initial message counters used only in bc frame auto-repeat mode. bc message block formats and bc control word in bc mode, the bu-65552, bu-65551 and bu-65550 support all mil-std-1553 message formats. for each 1553 message for- mat, the bu-65552, bu-65551 and bu-65550 mandate a specif- ic sequence of words within the bc message block. this includes locations for the control, command and (transmitted) data words that are to be read from ram by the bc protocol logic. in addition, subsequent contiguous locations must be allo- cated for storage of received loopback, rt status and data words. figure 9 illustrates the organization of the bc message blocks for the various mil-std-1553 message formats. note that for all of the message formats, the bc control word is located in the first location of the message block. for each of the bc message block formats, the first word in the block is the bc control word. the bc control word is not trans- mitted on the 1553 bus. instead, it contains bits that select the active bus and message format, enable off-line self-test, masking of status word bits, enable retries and interrupts, and specify mil-std-1553a or -1553b error handling. the bit mapping and definitions of the bc control word are illustrated in table 9. the bc control word is followed by the command word to be transmitted, and subsequently by a second command word (for an rt-to-rt transfer), followed by data words to be transmitted (for receive commands). the location after the last word to be transmitted is reserved for the loopback word. the loopback word is an on-line self-test feature. the subsequent locations after the loopback word are reserved for received status words and data words (for transmit commands). automatic retries the bu-65552, bu-65551 and bu-65550 bc implements auto- matic message retries. when enabled, retries will occur, follow- ing response timeout or format error conditions. as additional options, retries may be enabled when the message error status word bit is set by a 1553a rt or following a "status set" condi- tion. for a failed message, either one or two message retries will occur, the bus channel (same or alternate) is independently pro- grammable for the first and second retry attempts. retries may be enabled or disabled on an individual message basis. bc interrupts bc interrupts may be enabled by the interrupt mask register for stack rollover, retry, end-of-message (global), end-of- message (in conjunction with the bc control word for individual messages), response timeout, message error, end of bc frame, and status set conditions. the definition of "status set" is pro- grammable on an individual message basis by means of the bc control word. this allows for masking ("care/don't care") for the individual rt status word bits. 17 bc-to-rt transfer control word receive command word data word #1 data word #2 . . . last data word last data word looped back status received last data word . . . data word #2 data word #1 status received transmit command word control word rt-to-bc transfer transmit command looped back rx rt status word last data . . . data #2 data #1 tx rt status word transmit command receive command control word rt-to-rt transfer mode command looped back status received mode command control word mode code; no data mode command looped back data word status received tx mode command control word tx mode code; with data tx command looped back last data . . . data #2 data #1 tx rt status word tx command rx broadcast command control word rt-to-rts (broadcast) transfer last data looped back last data . . . data #2 data #1 broadcast command control word broadcast data word data word looped back status received rx mode command control word rx mode code; with data broadcast mode command looped back broadcast mode command control word broadcast mode code; no data data word looped back data word broadcast mode command control word broadcast mode code; with data figure 9. bc message block formats transmit command looped back remote terminal (rt) architecture the rt protocol design of the bu-65552, bu-65551 and bu- 65550 represent ddc's fifth generation implementation of a 1553 rt. one of the salient features of the ace's rt architec- ture is its true multiprotocol functionality. this includes program- mable options for support of mil-std-1553a, the various mcair protocols, and mil-std-1553b notice 2. the bu-65552, bu- 65551 and bu-65550 rt response time is 2 to 5 s dead time (4 to 7 s per 1553b), providing compliance to all the 1553 proto- cols. additional multiprotocol features include options for full software control of rt status and built-in-test (bit) words. alternatively, for 1553b applications, these words may be for- mulated in real-time by the bu-65552, bu-65551 and bu-65550 protocol logic. the bu-65552, bu-65551 and bu-65550 rt pro- tocol design implements all the mil-std-1553b message for- mats and dual redundant mode codes. this design is based largely on previous generation products that have passed seafac testing for mil-std-1553b compliance. the ace rt performs comprehensive error checking, word and format vali- dation, and checks for various rt-to-rt transfer errors. other key features rt include a set of interrupt conditions, internal command illegalization, and programmable busy by subaddress. rt memory organization table 27 illustrates a typical memory map for the bu-65552, bu-65551 and bu-65550 in rt mode. as in bc mode, the two stack pointers reside in fixed locations in the shared ram address space: address 0100 (hex) for the area a stack pointer and address 0104 for the area b stack pointer. besides the stack pointer, for rt mode there are several other areas of the ace address space designated as fixed locations. all rt modes of operation require the area a and area b lookup tables. also allocated, are several fixed locations for optional features: command illegalization lookup table, mode code selective interrupt table, mode code data table, and busy bit lookup table. it should be noted that any unenabled optional fixed loca- tions may be used for general purpose storage (data blocks). the rt lookup tables, which provide a mechanism for mapping data blocks for individual tx/rx/bcst-subaddresses to areas in the ram, occupy address range locations are 0140 to 01bf for area a and 01c0 to 023f for area b. the rt lookup tables include subaddress control words and the individual data block pointers. if used, address range 0300-03ff will be dedicated as the illegalizing section of ram. the actual stack ram area and the individual data blocks may be located in any of the nonfixed areas in the shared ram address space. rt memory management another salient feature of the ace series products is the flexibil- ity of its rt memory management architecture. the rt archi- tecture allows the memory management scheme for each trans- mit, receive, or broadcast subaddress to be programmable on a subaddress basis. also, in compliance with mil-std-1553b notice 2, the bu-65552, bu-65551 and bu-65550 provide an option to separate data received from broadcast messages from nonbroadcast received data.besides supporting a global double buffering scheme (as in bc mode), the ace rt provides a pair of 128-word lookup tables for memory management control, programmable on a subaddress basis (refer to table 28). the 128-word tables include 32-word tables for transmit message pointers and receive message pointers. there is also a third, optional lookup table for broadcast message pointers, provid- ing notice 2 compliance, if necessary. the fourth section of each of the rt lookup tables stores the 32 subaddress control words (refer to table 10 and 28). the individual subaddress control words may be used to select the rt memory management option and interrupt scheme for each transmit, receive, and (optionally) broadcast subaddress. for each transmit subaddress, there are two possible memory management schemes: (1) single message; and (2) circular buffer. for each receive (and optionally broadcast) subaddress, there are three possible memory management schemes: (1) sin- gle message; (2) double buffered; and (3) circular buffer. for each transmit, receive and broadcast subaddress, there are two interrupt conditions programmable by the respective subaddress control word: (1) after every message to the sub- address; (2) after a circular buffer rollover. an additional table in ram may be used to enable interrupts following selected mode code messages. when using the circular buffer scheme for a given subaddress, the size of the circular buffer is programmable by three bits of the 18 data block 356 2fe0-2fff ? ? ? ? ? ? data block 6 0420-043f data block 5 0400-041f command illegalizing table (fixed area) 0300-03ff reserved data block 1-4 0280-02ff data block 0 0260-027f (not used) 0248-025f busy bit lookup table (fixed area) 0240-0247 lookup table b (fixed area) 01c0-023f lookup table a (fixed area) 0140-01bf mode code data (fixed area) 0110-013f mode code selective interrupt table (fixed area) 0108-010f stack pointer b (fixed location) 0104 reserved 0101-0103 stack pointer a (fixed location) 0100 stack a 0000-00ff description address (hex) 0105-0107 table 27. typical rt memory map (shown for 12k ram) notes: 1) address represents the word offset from the memory base address in the common memory address space. 3) for the 65552, the memory spans from 0000(hex) to ffff(hex), providing a full 64k words of shared ram. subaddress control word (see table 29). the options for cir- cular buffer size are 128, 256, 512, 1024, 2048, 4096, and 8192 data words. single message mode figure 10 illustrates the rt single message memory manage- ment scheme. when operating in default mode, the single message scheme is implemented for all transmit, receive, and broadcast subaddresses. in the single message mode (also in the double buffer and circular buffer modes), there is a global double buffering scheme, controlled by bit 13 of configuration register #1. this selects from between the two sets of the vari- ous data structures shown in the figure: the stack pointers (fixed addresses), descriptor stacks (user defined addresses), rt lookup tables (fixed addresses), and rt data word blocks (user defined addresses). figures 27, 28, and 29 delineate the "active" and "nonactive" areas by the non-shaded and shaded areas, respectively. as shown, the ace stores the command word from each mes- sage received, in the fourth location within the message descrip- tor (in the stack) for the respective message. the bit, sub- address field, and (optionally) broadcast/own address, index into the active area lookup table, to locate the data block pointer for the current message. rt memory management logic then accesses the data block pointer to locate the starting address for the data word block for the current message. the maximum size for an rt data word block is 32 words. for a particular subaddress in the single message mode, there is overwriting of the contents of the data blocks for receive/broadcast subaddresses ? or overreading, for transmit subaddresses. in the single message mode, it is possible to access multiple data blocks for the same subaddress. this, how- ever, requires the intervention of the host processor to update the respective lookup table pointer. to implement a data wraparound subaddress, as required by notice 2 of mil-std-1553b, the single message scheme should be used for the wrap-around subaddress. notice 2 recommends subaddress 30 as the wraparound subaddress. circular buffer mode figure 11 illustrates the rt circular buffer memory manage- ment scheme. the circular buffer mode facilitates bulk data transfers. the size of the rt circular buffer, shown on the right side of the figure, is programmable from 128 to 8192 words (in even powers of 2) by the respective subaddress control word. as in the single message mode, the host processor initially loads the individual lookup table entries. at the start of each mes- sage, the ace stores the lookup table entry in the third position of the respective message block descriptor in the stack area of ram, as in the single message mode. the ace transfers receive or transmit data words to (from) the circular buffer, starting at the location referenced by the lookup table pointer. at the end of a valid (or, optionally, invalid) message, the value of the lookup table entry updates to the next location after the last address accessed for the current message. as a result, data words for the next message directed to the same tx/rx(/bcst) subaddress will be accessed from the next contiguous block of address locations within the circular buffer. as a recommended option, the lookup table pointers may be programmed to not update following an invalid receive (or broadcast) message. this allows the 1553 bus controller to retry the failed message, result- ing in the valid (retried) data overwriting the invalid data. this eliminates overhead for the rt's host processor. when the pointer reaches the lower boundary of the circular buffer (locat- ed at 128-, 256-, . . . 8192-word boundaries in the address space), the pointer moves to the top boundary of the circular buffer, as figure 11 shows. implementing bulk data transfers the use of the circular buffer scheme is ideal for bulk data trans- fers; that is, multiple messages to/from the same subaddress. the recommendation for such applications is to enable the cir- cular buffer interrupt request. by so doing, the routine transfer of multiple messages to the selected subaddress, including errors and retries , is transparent to the rt's host processor. by strategically initializing the subaddresses' lookup table pointer r / t 19 circular buffer of specified size 8192-word 1 1 1 4096-word 0 1 1 1024-word 0 0 1 512-word 1 1 0 256-word 0 1 0 128-word 1 0 0 single message or double buffered 0 0 0 comment description mm0 mm1 mm2 table 29. subaddress control word memory management subaddress buffer scheme 2048-word 1 0 1 subaddress control word lookup table (optional) sacw_sa0 . . . sacw_sa31 0220 . . . 023f 01a0 . . . 01bf broadcast lookup table (optional) bcst_sa0 . . . bcst_sa31 0200 . . . 021f 0180 . . . 019f transmit lookup table tx_sa0 . . . tx_sa31 01e0 . . . 01ff 0160 . . . 017f receive (/broadcast) lookup table rx(/bcst)_sa0 . . . rx(/bcst)_sa31 01c0 . . . 01df 0140 . . . 015f comment description area b area a table 28. rt look-up tables note: address represents the word offset from the memory base address in the common memory address space. 20 figure 10. rt memory management: single message mode data blocks data block data block block status word time tag word data block pointer received command word descriptor stacks look-up table addr look-up table (data block addr) 15 13 0 current area b/a configuration register stack pointers circular buffer rollover 15 13 0 received (transmitted) message data (next location) 128, 256 8192 words pointer to current data block pointer to next data block look-up table entry circular data buffer look-up tables look-up table address block status word time tag word data block pointer received command word configuration register stack pointers descriptor stack current area b/a tx/rs/bcst_sa look-up table entry is updated following valid receive (broadcast) message or following completion of transit message. * * figure 11. rt memory management: circular buffer mode 21 prior to the start of the bulk transfer, the bu-65550 and bu-65551 may be configured to issue an interrupt request only after it has received the anticipated number of valid data words to the designated subaddress. subaddress double buffering mode for receive (and broadcast) subaddresses, the bu-65552, bu- 65551 and bu-65550 rt offer a third memory management option, subaddress double buffering. subaddress double buffering provides a means of ensuring data consistency. figure 12 illustrates the rt subaddress double buffering scheme. like the single message and circular buffer modes, the double buffering mode may be selected on a subaddress basis by means of the subaddress control word. the purpose of the double buffering mode is to provide the host processor a convenient means of accessing the most recent, valid data received to a given subaddress. this serves to ensure the high- est possible degree of data consistency by allocating two 32-bit data word blocks for each individual receive (and/or broadcast) subaddress. at a given point in time, one of the two blocks will be designated as the "active" 1553 data block while the other will be designat- ed as the "inactive" block. the data words from the next receive message to that subaddress will be stored in the "active" block. upon completion of the message, provided that the message was valid and subaddress double buffering is enabled, the bu- 65552, bu-65551 and bu-65550 will automatically switch the "active" and "inactive" blocks for the respective subaddress. the ace accomplishes this by toggling bit 5 of the subaddresses' lookup table pointer and rewriting the pointer. as a result, the most recent valid block of received data words will always be readily accessible to the host processor.as a means of ensuring data consistency, the host processor is able to reliably access the most recent valid, received data word block by performing the following sequence: (1) disable the double buffering for the respective subad- dress by the subaddress control word. that is, temporarily switch the subaddresses' memory management scheme to the single message mode. (2) read the current value of the receive (or broadcast) sub- address's lookup table pointer. this points to the current "active" data word block. by inverting bit 5 of this pointer value, it is possible to locate the start of the "inactive" data word block. this block will contain the data words received during the most recent valid message to the subaddress. (3) read out the words from the "inactive" (most recent) data word block. (4) re-enable the double buffering mode for the respective subaddress by the subaddress control word. rt interrupts as in bc mode, the bu-65552, bu-65551 and bu-65550 rt provide many maskable interrupts. rt interrupt conditions include end of (every) message, message error, selected subaddress (subaddress control word) interrupt, circular buffer rollover, selected mode code interrupt, and stack rollover. 15 13 0 block status word time tag word data block pointer received command word configuration register stack pointers descriptor stack current area b/a data blocks data block 1 data block 0 x..x 0 yyyyy x..x 1 yyyyy receive double buffer enable subaddress control word msb data block pointer look-up tables figure 12. rt memory management: subaddress double buffering mode 22 descriptor stack at the beginning and end of each message, the bu-65552, bu- 65551 and bu-65550 rt stores a four-word message descriptor in the active area stack. the rt stack size is programmable, with choices of 256, 512, 1024, and 2048 words. figures 5, 6 and 7 show the four words: block status word, time tag word, data block pointer, and the 1553 received command word. the rt block status word includes indications of message in- progress or message complete, bus channel, rt-to-rt transfer and rt-to-rt transfer errors, message format error, loop test (self-test) failure, circular buffer rollover, illegal command, and other error conditions. table 23 shows the bit mapping of the rt block status word. as in bc mode, the time tag word stores the current contents of the bu-65552, bu-65551 and bu-65550 read/writable time tag register. the resolution of the time tag register is pro- grammable from among 2, 4, 8, 16, 32, and 64 s/lsb. also, incrementing of the time tag counter may be from an external clock source or via software command. the ace stores the contents of the accessed lookup table location for the current message, indicating the starting location of the data word block, as the data block pointer. this serves as a convenience in locating stored message data blocks. the ace stores the full 16-bit 1553 command word in the fourth location of the rt message descriptor. rt command illegalization the bu-65552, bu-65551 and bu-65550 provide an internal mechanism for rt command illegalization. in addition, there is a means for allowing the setting of the busy status word bit to be only for a programmed subset of the transmit/receive/broadcast subaddresses. the illegalization scheme uses a 256-word area in the shared ram address space. a benefit of this feature is the reduction of printed circuit board requirements, by eliminating the need for an external prom, pld, or ram device that does the illegalizing function. the bu-65552, bu-65551 and bu-65550 illegalization scheme provides maximum flexibility, allowing any subset of the 4096 possible combinations of broadcast/own address, bit, subaddress, and word count/mode code to be illegalized. another advantage of the ram-based illegalization technique is that it provides for a high degree of self-test ability. addressing the illegalization table table 30 illustrates the addressing scheme of the illegalization ram . as shown, the base address of the illegalizing ram is word address 0300 (hex) in the shared ram. the ace formu- lates the index into the illegalizing table based on the values of broadcast/own address, bit, subaddress, and the msb of the word count/mode code field (wc/mc4) of the cur- rent command word. the internal ram has 256 words reserved for command illegal- ization. broadcast commands may be illegalized separately from non-broadcast receive commands and mode commands. r / t r / t commands may be illegalized down to the word count level. for example, a one-word receive command to subaddress 1 may be legal, while a two-word receive command to subaddress 1 may be illegalized. the first 64 words of the illegalization table refer to broadcast receive commands (two words per subaddress). the next 64 words refer to broadcast transmit commands. since nonmode code broadcast transmit commands are by definition invalid, this section of the table (except for subaddresses 0 and 31) does not need to be initialized by the user. the next 64 words correspond to nonbroadcast receive commands. the final 64 words refer to nonbroadcast transmit commands. messages with word count/ mode code (wc/mc) fields between 0 and 15 may be illegalized by setting the corresponding data bits for the respective even- numbered address locations in the illegalization table. likewise, messages with wc/mc fields between 16 and 31 may be ille- galized by setting the corresponding data bits for the respective odd-numbered address locations in the illegalization table. the following should be noted with regards to command illegal- ization: (1)to illegalize a particular word count for a given broad- cast/own address- subaddress, the appropriate bit posi- tion in the respective illegalization word should be set to logic 1. a bit value of logic 0 designates the respective command word as a egal command. the bu-65552, bu-65551 and bu-65550 will respond to an illegalized non-broadcast com- mand with the message error bit set in its rt status word. (2)for subaddresses 00001 through 11110, the "wc/mc" field specifies the word count field of the respective command word. for subaddresses 00000 and 11111, the r / t wc4/mc4 0 (lsb) sa0 1 sa1 2 0 sa2 3 sa3 4 sa4 5 t/r 6 broadcast/ownaddress 7 1 8 1 9 0 10 0 12 0 13 0 14 0 15 (msb) description bit 11 table 30. illegalization ram address definition 23 "wc/mc" field specifies the mode code field of the respec- tive command word. (3)since nonmode code broadcast transmit messages are not defined by mil-std-1553b, the 60 words in the illegal- ization ram, addresses 0342 through 037d, corresponding to these commands do not need to be initialized. they will not respond to a non-mode code broadcast transmit com- mand, but will automatically set the message error bit in its internal status register, regardless of whether or not corre- sponding bit in the illegalization ram has been set. if the next message is a transmit status or transmit last command mode code, they will respond with its message error bit set. programmable busy as a means of providing compliance with notice 2 of mil-std- 1553b, the bu-65552, bu-65551 and bu-65550 rt provide a software controllable means for setting the busy status word bit as a function of subaddress. by a busy lookup table in the shared ram space, it is possible to set the busy bit based on command broadcast/own address, bit, and subaddress. another programmable option, allows received data words to be either stored or not stored for messages, when the busy bit is set. other rt functions the bu-65552, bu-65551 and bu-65550 allow the hardwired rt address to be read by the host processor. also, there are options for the rt flag status word bit to be set under soft- ware control and/or automatically following a failure of the loop- back self-test. other software controllable rt options include software programmable rt status and rt bit words, automat- ic clearing of the service request status word bit following a transmit vector word mode command, capabilities to clear and/or load the time tag register following receipt of synchronize mode commands, options regarding data word transfers for the busy and/or message error (illegal) status word bits, and for handling of 1553a and reserved mode codes. monitor (mt) architecture the bu-65552, bu-65551 and bu-65550 provide three bus monitor (mt) modes: (1) the "aim-hy" (default) or "aim-hy'er" word monitor mode. (2) a selective message monitor mode. (3) a simultaneous remote terminal/selective message monitor mode. the strong recommendation for new applications is the use of the selective message monitor, rather than the word monitor. besides providing monitor filtering based on rt address, bit, and subaddress, the message monitor eliminates the need to determine the start and end of messages by software. the development of such software tends to be a tedious task. moreover, at run time, it tends to entail a high degree of cpu overhead. r / t r / t word monitor in the word monitor mode, the bu-65552, bu-65551 and bu- 65550 monitor both 1553 buses. after initializing the word monitor and putting it on-line the bu-65552, bu-65551 and bu- 65550 store all command, status, and data words received from both buses. for each word received from either bus, a pair of words are stored in shared ram. the first word is the 16 bits of data from the received word. the second word is the monitor identification (id), or "tag" word. the id word contains informa- tion relating to bus channel, sync type, word validity, and inter- word time gaps. the bu-65552, bu-65551 and bu-65550 store data and id words in a circular buffer in the shared ram address space. table 24 shows the bit mapping for the monitor id word. monitor trigger word there is a trigger word register that provides additional flexi- bility for the word monitor mode. the bu-65552, bu-65551 and bu-65550 store the value of the 16-bit trigger word in the mt trigger word register. the contents of this register represent the value of the trigger command word. there are programma- ble options to start or stop the word monitor, and/or to issue an interrupt request following receipt of the trigger command word from the 1553 bus. selective message monitor mode the bu-65552, bu-65551 and bu-65550 selective message monitor provide features to greatly reduce the software and pro- cessing burden of the host cpu. the selective message monitor implements selective monitoring of messages from a dual 1553 bus, with the monitor filtering based on the rt address, bit, and subaddress fields of received 1553 command words. the selective message monitor mode greatly simplifies the host processor software by distinguishing between command and status words. the selective message monitor maintains two stacks in ram: a command stack and a data stack. simultaneous rt/message monitor mode the selective message monitor may function as a purely passive monitor or may be programmed to function as a simultaneous rt/monitor. the rt/monitor mode provides complete remote terminal (rt) operation for the bu-65552, bu-65551 and bu- 65550 strapped rt address and bus monitor capability for the other 30 nonbroadcast rt addresses. this allows it to simulta- neously operate as a full function rt and "snoop" on all or a sub- set of the bus activity involving the other rts on a bus. this type of operation is sometimes needed to implement a backup bus controller. the combined rt/selective monitor maintains three stack areas in the address space: an rt command stack, a monitor command stack, and a monitor data stack. the point- ers for the various stacks have fixed locations in the shared ram address space. selective message monitor memory organization table 31 illustrates a typical memory map for the ace in the selective message monitor mode. this mode of operation defines several fixed locations in the ram. these locations allo- cate in a manner that is compatible with the combined rt/selective message monitor mode. refer to figure 13 for an example of a typical selective message monitor memory map. r / t 24 the fixed memory map consists of two monitor command stack pointers (location 102h and 106h), two monitor data stack pointers (locations 103h and 107h), and a selective message monitor lookup table (0280-02ffh) based on rt address, , and subaddress. assume a monitor command stack size of 1k words, and a monitor data stack size of 2k words refer to figure 13 for an illustration of the selective message monitor operation. upon receipt of a valid command word, the bu-65552, bu-65551 and bu-65550 will reference the selective monitor lookup table (a fixed block of addresses) to check for the condition (disabled/enabled) of the current command. if dis- abled, it will ignore (and not store) the current message; if enabled, it will create an entry in the monitor command stack at the address location referenced by the monitor command stack pointer. similar to rt mode, the ace stores a block status word, 16-bit time tag word, and data block pointer in the message descriptor, along with the received 1553 command word fol- lowing reception of the command word. the ace writes the block status and time tag words at both the start and end of the message. the monitor block status word contains indica- tions of message in-progress or message complete, bus chan- nel, monitor data stack rollover, rt-to-rt transfer and rt-to- rt transfer errors, message format error, and other error condi- tions. r / t monitor command stack pointer b (fixed location) monitor command stack b 0800-0bff monitor command stack a 0400-07ff notes: 1) address represents the word offset from the memory base address in the common memory address space. 3) for the 65552, the memory spans from 0000(hex) to ffff(hex), providing a full 64k words of shared ram. 2000-2fff monitor data stack b not used 0300-03ff monitor data stack a selective monitor lookup table (fixed area) 1000-1fff 0280-02ff not used registers 0c00-0fff 0260-027f monitor data stack pointer b (fixed location) 0107 not used 0104-0105 monitor data stack pointer a (fixed location) 0103 monitor command stack pointer a (fixed location) 0102 not used 0000-0101 description address (hex) 0106 table 31. typical selective message monitor memory map (shown for 12k ram) 15 13 0 block status word time tag word data block pointer received command word configuration register #1 monitor command stack pointers monitor command stacks current area b/a monitor data stacks monitor data block #n + 1 monitor data block #n current command word monitor data stack pointers if this bit is "0" (not selected) no words are stored in either the command stack or data stack. in addition, the command and data stack pointers will not be updated. note selective monitor lookup tables selective monitor enable (see note) offset based on rta4-rta0, t/r, sa4 figure 13. selective message monitor memory management 25 table 25 shows the message monitor block status word. the data block pointer references the first word stored in the monitor data stack (the first word following the command word) for the current message. the will then proceed to store the subsequent words from the message (possible second command word, data word(s), status word(s) into consecutive locations in the monitor data stack. the size of the monitor command stack is programmable to 256, 1k, 4k, or 16k words. the monitor data stack size is pro- grammable to 512, 1k, 2k, 4k, 8k, 16k, 32k, or 64k words. monitor interrupts may be enabled for monitor command stack rollover, monitor data stack rollover, and/or end-of-message conditions. in addition, in the word monitor mode there may be an interrupt enabled for a monitor trigger condition. interface to mil-std-1553 bus figures 9 through 14 illustrates the interface from the bu- 65552, bu-65551 and bu-65550 to a 1553 bus for either trans- former (long stub) or direct (short stub) coupling, plus the peak- to-peak voltage levels that appear at various points (when trans- mitting). both coupling configurations require the use of an included cable assembly that interfaces directly to the pc card. for the transformer (long stub) coupling configuration, a second transformer, referred to as a coupling transfer is required. in accordance with mil-std-1553b, the turns ratio of the coupling transformer is 1.0 to 1.4. both transformer and direct coupling configurations require an isolation resistor to be placed in series with each leg of the trans- former connecting to the 1553 bus; this protects the bus against short circuit conditions in the transformers, stubs, or terminal components. the standard cable provided with the bu-65552 (part number ddc-70093-1), bu-65551 (part number ddc-58708-1) and bu-65550 (part number ddc-57612) provide for a transformer coupled connection. the mating connector required on the stub cable is a trompeter pl75 or equivalent connector. direct cou- pling requires the use of a optional cable assembly (ddc-70093- 1 for bu-65552, ddc-57613 for bu-65550, contact factory for bu-65551 cable assembly availability). bu-65550 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 data bus z 0 z 0 1:1.4 0.75 z 0 0.75 z0 bus coupler 1:1.79 1:1.79 bus a bus b ddc-57612-1 cable assembly (furnished with bu-65550) ddc-57613-1 cable assembly 20 ft. max trompeter cj70 cable jack transformer coupled or 1: 2.5 1: 2.5 bus a bus b direct coupled 1 ft. max 55 ? 55 ? 55 ? 55 ? 20v p-p 28v p-p 7v p-p trompeter pl75 or equivalent connector stub figure 14. bu-65550 interface to a mil-std-1553 bus 26 18.5 (0.47 meter) 1.158 (29.44) cable assy (mates with j1) connector, plug (2 reqd) trompeter p/n cj70-47 or equivalent 3.370 0.008 (85.59 0.20) 2.126 0.004 (54.00 0.10) 0.197 max (5.00 max) pin 34 pin 1 pin 35 p1 pin 68 b b pin 15 j1 pin 1 a a note: dimensions in inches(mm) unless otherwise noted. figure 15. bu-65550 mechanical outline, shown with standard ddc-57612-1 interface cable assemly 27 ace ace 1:1.79 1:1.79 transformer coupled 33 pin connector p2 p3 bus coupler bu-65551 trompeter pl75 or equivalent connector 1:1.4 0.75z 0 28v 7v p.p p.p data bus z 0 z 0 20 ft. max. 1:2.5 1:2.5 33 pin connector p2 p3 bu-65551 19" direct coupled 55w 55w 55w 55w ddc-58708-1 p1 p1 trompeter cj70-47 connector figure 16. bu-65551 interface to a mil-std-1553 bus 28 19 ( 0.487 meter ) 3.370 0.008 (85.59 0.20) 2.126 0.004 (54.00 0.10) 0.197 max (5.00 max) pin 34 pin 1 pin 35 p1 pin 68 b b a pin 1 pin 33 j1 a cable assy connector, plug (2 reqd) trompeter p/n cj70-47 or equiv alent ddc-58708-1 33 pin connector note: dimensions are in inches(mm) unless otherwise noted. figure 17. bu-65551 mechanical outline, shown with standard ddc-58708-1 interface cable assemly 29 19 ( 0.487 meter ) 3.370 0.008 (85.59 0.20) 2.126 0.004 (54.00 0.10) 0.197 max (5.00 max) pin 34 pin 1 pin 35 p1 pin 68 b b a pin 1 pin 33 j1 a cable assy connector, plug (2 reqd) trompeter p/n cj70-47 or equiv alent ddc-70093-1 33 pin connector note: dimensions are in inches(mm) unless otherwise noted. figure 18. bu-65552 mechanical outline, shown with standard ddc-70093-1 interface cable assemly 30 ce mark certification the bu-65551m2-300 and the BU-65552M2-300 carry the ce mark signifying conformance to the requirements of council directive 89/336 eec. the supporting test (reports) are on file at ddc, new york, usa and are available for on-site review. 31 ordering information bu-xxxxxmx-300 test criteria: 0 = none screening: 0 = standard ddc procedures temperature range: bu-65552 series = 0 to +55 c bu-65550 series = 0 to +55 c bu-65551 series = -25 to +70 c cable type: 0 = without cable 1 = direct coupled * 2 = transformer coupled ** package: m = module product type: 65552 = bc/rt/mt with 64k ram, isolation transformer inside interface card assembly. 65551 = bc/rt/mt with 4k ram, isolation transformer inside interface card assembly. 65550 = bc/rt/mt with 12k ram, isolation transformers part of cable assembly. * contact factory for direct coupled cable assembly for bu-65552 series ** includes ddc-70093-1, transformer coupled cable assembly for bu-65552 series. . * contact factory for direct coupled cable assembly for bu-65551 series. ** includes ddc-58708-1, transformer coupled cable assembly for bu-65551 series. * includes ddc-57613-1, direct coupled cable assembly for bu-65550 series. ** includes ddc-57612-1, transformer coupled cable assembly for bu-65550 series. standard software: bus-69080 - 16-bit ? c ? library bus-69081 - windows 3.1 menu bus-69082 - 32-bit windows 95 dll/driver bus-69083 - 32-bit windows 95 nt dll/driver bus-69084 - 32-bit windows 95 menu bus-69085 - 32-bit windows 95 nt menu 32 g-05/00-0 printed in the u.s.a. the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7382 or 7234 headquarters - tel: (631) 567-5600, fax: (631) 567-7358 west coast - tel: (714) 895-9777, fax: (714) 895-4988 southeast - tel: (703) 450-7900, fax: (703) 450-6610 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)8141-349-087, fax: +49-(0)8141-349-089 sweden - tel: +46-(0)8-54490044, fax +46-(0)8-7550570 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com |
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